1. Field of the Invention
The present invention generally relates to a memory device, and more particularly to a nonvolatile memory device using semiconductor crystals and a method for making the same.
2. Description of the Related Art
Nonvolatile memory is ubiquitous in today's technology-laden world, and the most prevalent type of device used to store information is the flash memory.
In addition to the need for integrated nonvolatile memory in logic systems, there is a large (and rapidly increasing) market for flash memories as stand-alone storage elements. Cellular telephones and digital cameras are several examples of devices which benefit from nonvolatile flash memory cards.
There are various forecasts predicting increased future markets for this type of storage (e.g., see P. Pavan, R. Bez, P. Olivio, and E. Zanoni, IEEE Proc. 85 1248 (1997).
Flash memory is based on the concept of a field effect transistor (FET) whose threshold voltage (VT) can be reversibly changed between first and second values.
As shown in the side sectional view of FIG. 1(a), a conventional flash memory device 100 is shown including a substrate 101, source 102 and drain 103, formed in the substrate 101 with a channel 104 formed therebetween, a program oxide 105 formed over the substrate 101, a floating gate 106 formed over the program oxide 105, a control oxide 107 formed over the floating gate 106, and a control gate 108 formed over the control oxide 107.
A main component of the flash memory device 100 which facilitates this multi-state operation is a conducting floating gate 106 in the gate stack of the transistor (see FIG. 1(a)) which is coupled to its surroundings (the control gate 108, and also the channel 104/source 102/drain 103 regions) via dielectrics (e.g., 107, 105) on top and below.
The device 100 is programmed by injecting charge into the floating gate 106 (though the program oxide 105), and is erased by expelling charge from the floating gate 106. These devices 100 are made nonvolatile by decoupling the floating gate 106 from the source 102/drain 103/channel 104 and control gate 108 with a sufficiently thick control oxide 107.
As with all other semiconductor technologies, flash memory continues to scale to increasingly higher densities. At the same time, improvements in device speed, power consumption, and endurance (e.g., number of times the memory can be read/erased before failing) also pay obvious benefits.
Finally, some flash memory devices have improved performance through storage of multiple bits per memory cell (e.g., most notably Intel's StrataFlash™ technology currently stores 2 bits/cell with announced future plans to increase the number of bits/cell). This is achieved by programming the floating gate 106 with different amounts of charge in order to achieve multiple possible threshold voltage (VT) shifts in the same device.
The pathway to many of these density and performance benefits involves scaling the memory FET, which is becoming increasingly difficult. For example, shrinking the device width in order to improve packing density and speed results in increased drain turn-on effects from capacitive coupling between the drain 103 and the floating gate 106.
Also, thinning the program oxide 105 thickness in order to achieve lower write/erase voltages (and thus lower power) has the effect of reducing retention times and reliability.
Referring to FIG. 1(b), nanocrystal memory devices have been proposed as a way to improve the scaling of flash memory devices, and also as a possible means to achieve robust multi-bit operation (e.g., see H. Hanafi, IEEE Trans. Elect. Dev. 43 1553 (1996); S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. Crabbe, C. Chan, Appl. Phys. Lett. 68 1377 (1996); and S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, D. Buchanan, IEDM 521 (1995)).
Turning to the conventional nanocrystal memory device 150 shown in FIG. 1(b), the structure is somewhat similar to that shown in FIG. 1(a) except that the floating gate 106 is replaced with nanocrystals 156.
That is, a basic idea in nanocrystal memory devices is that breaking up a continuous, conducting floating gate 106 into small bits of isolated conducting material can aid in overcoming some of the roadblocks to further scaling.
The nanocrystal floating gate 156 has reduced capacitive coupling to the source 151/drain region 152, which leads to a smaller drain turn-on effect. In addition, the nanocrystal floating gate 106 should make the device less susceptible to stress-induced leakage current. That is, if an individual nanocrystal becomes shorted to the channel 154, other nanocrystals remain unaffected. In a standard floating gate device (e.g., such as device 100), any short to the channel 104 is disastrous because charge can no longer be maintained in the floating gate 106.
Nanocrystal floating gate devices (e.g., such as those exemplified by reference numeral 150 in FIG. 1(b)) have improved retention characteristics compared to conventional flash devices with the same program oxide thicknesses, because most charge leakage from the floating gate 156 occurs to the heavily doped source 152/drain regions 153.
In a flash device, such leakage will deplete charge from the entire floating gate, resulting in a loss of memory (e.g., in the same way as stress-induced leakage currents compromise the device).
In a nanocrystal device, only those nanocrystals in close proximity to the source 152/drain 153 lose their charge by this leakage mechanism, while those farther away (e.g., near the device center) do not. This argument assumes that there is no electrical conduction between nanocrystals in the floating gate 156 (e.g., a condition which can be controlled via the nanocrystal density).
The improved retention properties of nanocrystal floating gate devices 150 allows scaling to thinner program oxides 155, which can result in added benefits. Thinner oxides 155 permit programming at lower voltages using direct quantum mechanical tunneling, rather than Fowler-Nordheim field emission processes.
In addition to the obvious lower-power benefit of lower voltage operation, there is some evidence which suggests that a direct tunneling write/erase mechanism puts less stress on the program oxide 155, thereby resulting in increased device cyclability. Modeling also suggests that devices with thinner oxides 155 can be programmed more quickly (e.g., see M. She, Y. C. King, T. J. King, C. Hu, IEEE Device Research Conference, 139 (2001)).
One of the more intriguing aspects of nanocrystal memories 150 is the possibility to program the floating gate 156 with discrete numbers of electrons, which in turn leads to multiple discrete, well-defined device threshold voltage (VT) shifts. The idea is that the electrostatic energy necessary to add a single charge to a sufficiently small nanocrystal can become significant. This electrostatic charging energy is given by:
                    U        =                              e            2                                2            ⁢                          C              ∑                                                          (        1        )            where e is the electron charge and CΣ is the nanocrystal capacitance to its surroundings. Tiwari et al. have estimated this charging energy for different diameter nanocrystals (in this calculation, the nanocrystals were assumed to be spherical) (e.g., see S. Tiwari, J. A. Wahl, H. Silva, F. Rana, J. J. Welser, Appl. Phys. A 71 403 (2000)). The results are shown in Table 1. The charge stored in the floating gate will shift the device VT by an amount:
                              Δ          ⁢                                          ⁢                      V            T                          ≈                              -            Q                                C            ctl                                              (        2        )            where Q is the amount of charge stored on the floating gate 156 and Cctl is the floating gate capacitance to the control gate 158. Tiwari et al. have also computed the ΔVT for charge stored in different sized nanocrystals. These results are also shown in Table 1 below.
TABLE 1NanocrystalΔVT (for a singleDiameter (nm)Ec (eV)added charge) (V)30.011.0320.018.0610.036.235.072.82.178>5
Table 1 above illustrates a calculated charging energy (Ec) and corresponding threshold voltage shift (ΔVT) for nanocrystals of different sizes (e.g., from Tiwari et al., mentioned above).
Table 1 shows that the addition of a single charge to a nanocrystal can result in a significant threshold voltage shift (ΔVT˜0.5 V for a nanocrystal diameter between 5–10 nm). In this way, it may be possible to use this effect for multi-bit storage, where discrete VT shifts correspond to adding incrementally larger numbers of charges to the floating gate 156. These types of discrete VT shifts from adding single charges have been seen experimentally in extremely small devices in which the floating gate 156 contains only a single nanocrystal (e.g., see J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, Y. Lee, IEEE Elect. Dev. Lett. 18 278 (1997).
In more conventional devices where the floating gate 156 contains many nanocrystals (e.g., instead of a single one), effects due to discrete charging are usually averaged out due to nanocrystal size distributions.
In order to observe this effect (and thus make possible multi-bit storage in the device), it is essential to define all nanocrystals to be of similar size.
Several groups have demonstrated implementations of nanocrystal-based flash memories. However, none has defined all nanocrystals to be of similar size by using a self-assembly technique. Tiwari et al. have published numerous papers and also hold a patent (e.g., see U.S. Pat. No. 5,714,766, incorporated herein by reference) on a memory device based on CVD-deposited silicon nanocrystals.
Kim et al. have also published results on a similar device (e.g., see I. Kim et al., IEEE Electon Dev. Lett. 20 630 (1999)). Welser et al. (e.g., see above-mentioned J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, Y. Lee, IEEE Elect. Dev. Lett. 18 278 (1997), have demonstrated a memory device based on a single nanocrystal in the floating gate. This type of device is often called a “quantum dot memory”. Chou et al. also hold a patent on this device structure (e.g., see U.S. Pat. No. 6,069,380, incorporated herein by reference).
Ostraat et al. have described operation of a memory device in which the floating gate contains aerosol-deposited silicon nanocrystals (e.g., see M. L. Ostraat et al., Appl. Phys. Lett. 79 433 (2001)).
Finally, King et al. have described a device containing germanium nanocrystals (e.g., see. Y. C. King, T. J. King, C. Hu, IEDM, 155 (1998)).
However, in each of these conventional demonstrations, the nanocrystal sizes were not well-defined, thereby leading to limitations on device performance improvements.
Additionally, as mentioned above and prior to the present invention, nanocrystal floating gate memories have been difficult to use for multi-bit memory applications, because of the large nanocrystal size distributions.
Further, prior to the present invention, defining all nanocrystals to be of substantially similar size (and thus making possible multi-bit storage in the device), has not been achieved.
Moreover, there has been no technique which produces a nanocrystal memory device having nanocrystal size distributions which are substantially uniform, using a self-assembly technique.
In sum, the conventional techniques (and subsequently the resulting structure) to make a nanocrystal memory have been notoriously unreliable, and it has been difficult to obtain uniform size of the nanocrystals, and difficult to control the spacing of the distribution around the sample, each of which impact the performance of the device.